The present invention relates to a semiconductor memory device provided with a data compression test function and its testing method.
With the trend toward higher integration for semiconductor memory devices, the time required for their memory tests has been increasing. If the memory capacity increases four times, for instance, the testing time will be quadrupled, too. In addition, if the number of bits in one word in a semiconductor memory device is high, the number of semiconductor memory devices that can be tested simultaneously on one testing apparatus becomes restricted. Thus, in order to reduce the testing time by increasing the simultaneous testing capacity, there are semiconductor memory devices provided with a data compression test function.
FIG. 6 shows the principle structure of a semiconductor memory device of this type in the prior art.
This semiconductor memory device is provided with memory blocks 10 to 13 which are all structured identically. Address specification is made by a row decoder 14 and a column decoder 15, which are commonly shared by the memory blocks 10 to 13. RA is a row address and CA is a column address. FIG. 7 shows the structure of the memory block 10.
During a data write in the memory test mode, four-bit data are provided to input/output terminals 20 to 23 in a state in which the outputs from distribution circuits 30 to 33 are validated and the output of matching detection circuits 40 to 43 are invalidated (at high impedance, for instance) by a control circuit 16. The data provided to the input/output terminals 20 to 23 are reproduced into identical four-bit data by distribution circuits 30 to 33 respectively, and then are written in the memory blocks 10 to 13 respectively. The outputs from the distribution circuits 30 to 33 are insulated from one another. In the memory block 10, the identical data on data lines D0 to D3 shown in FIG. 7, are provided to a memory cell array 101 via a column select switch circuit 103 and a sense amplifier 102 and are written over 4 columns, selected by the column decoder 15, in one row, selected by the row decoder 14.
During a data read in the memory test mode in FIG. 6, four-bit data are read out from the memory blocks 10 to 13 in a state in which the output of the distribution circuits 30 to 33 are set at high impedance and are then taken out at the data input/output terminals 20 to 23 via the matching detection circuits 40 to 43. In the memory block 10, one row in the memory cell array 101 shown in FIG. 7 is selected by the row decoder 14, its memory contents are provided to the column select switch circuit 103 via the sense amplifier 102, four bits in the one row are selected by the column decoder 15 and are provided to the matching detection circuit 40 via the data lines D0 to D3. During this operation, if the logical levels of the data lines D0 to D3 do not match, an NG decision is made for these four bits.
In a data compression test such as described above, it is possible to reduce the testing time, since, while there are four bits in one word, the test itself can be performed in units of sixteen bits.
FIG. 8 shows part of FIG. 7 in detail. In FIG. 7, for the sake of simplification, each data line is shown as a single line, in reality the data lines are doubled, as shown in FIG. 8, with D0 to D3 and *D0 to *D3, through which mutually complementary data are provided. Reference signs C000 to C131 indicate memory cells while reference characters T000 to T131 indicate transfer gates. Word lines WL00 to WL03 are connected to word lines WL 10 to WL13 respectively.
During a data write in the memory test mode, when the word lines WL00 and WL10 are selected by the row decoder 14 to turn ON the transfer gates T000, T001, T100 and T101 and the column line CL is selected by the column decoder 15 to turn ON the column select switch circuits 1030 and 1031, the data on the data lines Di and *Di (i=0 to 3) are amplified by a sense amplifier 102i and provided to the bit lines BLi and *BLi and the data on the bit lines BL0 to BL3 are written in the memory cells C000, C001, C100 and C101 respectively. Likewise, when the word lines WL01 and WL11 and the column line CL are selected, the data on the data lines D0 to D3 are written in the memory cells C010, C011, C110 and C111 respectively, when the word lines WL02 and WL12 and the column line CL are selected, the data on the data lines *D0 to *D3 are written in the memory cells C020, C021, C120 and C121 respectively and when the word lines WL03 and WL13 and the column line CL are selected, the data on the data lines *D0 to *D3 are written in the memory cells C030, C031, C130 and C131 respectively.
The data lines D0 to D3 are set to "1" (the data lines *D0 to *D3 are set to "0"), the column line CL is selected and then the word lines are selected sequentially. Identical processing is repeated for the other columns. This makes the test memory pattern in the memory cell array look as shown in FIG. 9A. The hatched rectangles in the figure are memory cells set to "1" while the unhatched rectangles are memory cells set to "0".
With this memory pattern, it is possible to detect a failure caused by the interference among memory cells that may occur when an electric charge leaks from the memory cells that are set to "1" into the memory cells that are set to "0", which are surrounded by memory cells set to "1", causing the memory cells that have been set to "0" to be switched to "1". A test can be performed in an identical manner in a reverse pattern in which "0" and "1" are reversed.
With the memory pattern shown in FIG. 9A, since the bit lines BL0, BL1, . . . are set to "1" in sequence, and not to "0", it is not possible to detect a failure caused by interference between memory cells and the bit lines, such as the memory cell C000 changing from "1" to "0" with the electric charge in the memory cell C000 leaking to the bit line BL0 in a state in which "1" has been written in the memory cell C000, the transfer gate T000 has been turned OFF and the bit line BL0 has been set to "0" in FIG. 8. This test can be performed while forming the memory pattern shown in FIG. 9B. For instance, the column line CL is selected to execute the following processing in sequence:
(1) selecting the word line WLD00 with D0="1" & D1="0" PA1 (2) selecting the word line WLD01 with D0="1" & D1="0" PA1 (3) selecting the word line WLD02 with D0="0" & D1="1" PA1 (4) selecting the word line WLD03 with D0="0" & D1="1"
BL0="0" when (3) and (4) above are performed, and interference between the memory cell C000 and the bit line BL0 and interference between the memory cell C010 and the bit line BL0 can be tested.
However, since, in the processing described above, the data compression method in the prior art, which has identical data on the data lines D0 to D4, cannot be employed, the test must be performed in the non-compression, normal operating mode, and the length of testing time becomes increased.